VSL 2014: VIENNA SUMMER OF LOGIC 2014
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PROGRAM
SYNT ON THURSDAY, JULY 24TH: TALK VIEW
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9:00
9:30
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11:00
11:30
12:00
12:30
13:00
13:30
14:00
14:30
15:00
15:30
16:00
16:30
09:00-10:15
Automatic Device Driver Synthesis Project: a Work-in-Progress Report (Invited Talk)
Leonid Ryzhyk
10:45-11:15
Parameterized Synthesis Case Study: AMBA AHB
Ayrat Khalimov, Swen Jacobs, Roderick Bloem
11:15-11:45
Are There Good Mistakes? A Theoretical Analysis of CEGIS
Susmit Jha, Sanjit A. Seshia
11:45-13:00
Petri Games: Synthesis of Distributed Systems with Causal Memory (Invited Talk)
Bernd Finkbeiner
14:45-15:15
AbsSynthe: abstract synthesis from succinct safety specifications
Romain Brenguier, Guillermo Perez, Ocan Sankur, Jean-Francois Raskin
15:15-15:45
Low-effort Specification Debugging and Analysis
Rüdiger Ehlers, Vasumathi Raman
10:15-10:45
Coffee Break
13:00-14:30
Lunch Break
16:00-16:30
Coffee Break
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