VSL 2014: VIENNA SUMMER OF LOGIC 2014

VSTTE ON THURSDAY, JULY 17TH: TALK VIEW

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10:45-11:45
Finding Security Vulnerabilities in a Network Protocol using Parameterized Systems
Orna Grumberg
11:45-12:10
A Model for Capturing and Replaying Proof Strategies
Leo Freitas, Cliff B. Jones, Andrius Velykis, Iain Whiteside
12:10-12:35
A Verification Condition Visualizer
Madiha Jami, Andrew Ireland
12:35-13:00
What Gives? A Hybrid Algorithm for Error Explanation
Vijayaraghavan Murali, Nishant Sinha, Emina Torlak, Satish Chandra
14:30-14:55
Efficient Refinement Checking in VCC
Sumesh Divakaran, Deepak D'Souza, Nigamanth Sridhar
14:55-15:20
Formalizing Semantics with an Automatic Program Verifier
Martin Clochard, Jean-Christophe Filliatre, Claude Marché, Andrei Paskevich
15:20-15:45
The KeY Platform for Verification and Analysis of Java Programs
Ahrendt et.al
15:45-16:00
Using Promela in a Fully Verified Executable LTL Model Checker (SHORT)
René Neumann
10:15-10:45 Coffee Break
13:00-14:30 Lunch Break
16:00-16:30 Coffee Break
16:30-17:30
Foundations and Technology Competitions Award Ceremony
Kurt Gödel Research Prize Fellowships Program
17:30-18:15
FLoC Olympic Games Award Ceremony 1
Floc Olympic Games
18:15-18:30
FLoC Closing Week 1
Helmut Veith
21:00-23:59 VSL Student Reception 1
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